In computer architecture, clock gating is a popular power management technique used in many synchronous circuits for reducing dynamic power dissipation (a significant source of power dissipation in digital designs), by removing the clock signal when the circuit, or a subpart of it, is idle. Clock gating saves power by pruning part of the clock tree distribution, at the cost of adding more logic to a circuit.
In computer architecture, clock gating is a popular power management technique used in many synchronous circuits for reducing dynamic power dissipation (a significant source of power dissipation in digital designs), by removing the clock signal when the circuit, or a subpart of it, is idle. Clock gating saves power by pruning part of the clock tree distribution, at the cost of adding more logic to a circuit.
Source: Wikipedia "Clock gating" · CC BY-SA 4.0
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